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| wasabi |
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By _edge - Posted on July 3, 2006 - 10:02:02 (#20073)
Current version when comment was posted: 0.1 |
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Hey Caz,
Wahrz mee Voohdoohtoo dryvers at yee lahnd luhber arrhh, just playin :)
Thanks for the nice prog man, 10 stars
-edge
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| Nice work |
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By zittergie - Posted on September 1, 2004 - 21:24:15 (#14065)
Current version when comment was posted: 0.1 |
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This really works fine.
I have an AMD Athlon XP 2100+ and without disabling SSE Mesa 6.1 didn't work, With this app I can keep SSE enabled and everything works fine.
Thanx Caz,
and thanx Philippe Houdoin for pointing me to this app (and for Mesa)
Zittergie
'BE the difference that makes a difference' - JEWEL
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| gcc versions |
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By Caz - Posted on June 15, 2003 - 16:51:08 (#7748)
Current version when comment was posted: 0.1 |
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Hi,
Yes SSE is guaranteed to be enabled or there would be an invalid opcode crash, R5 also does support SSE on Athlon Xp's too and detects it's there, but R5 does not enable bit 9 of cr4 causing the Athlon Xp problems.
gcc 2.95.3 supports the newer instructions like SSE and MMX+, probably the geekgadgets gcc does too, the original R5 supports MMX so you can use movq with it but not movntq, blah blah. gcc 2.95.3 also supports -fomit-frame-pointer properly, R5 original does not although no error is outputted.
You can use any compiler you like, gcc 2.95.3 generates the best code, just link to the original libstdc++.r4 if your using c++ iostream stuff, also i modified the file /boot/develop/headers/cpp/streambuf.h to stop compile errors with gcc 2.95.3, right at the bottom of this file i changed this, there are a few things that gcc 2.95.3 has problems with, some apps which i used vectors in crash on startup, but were ok with R5 original.
if (_arrays) { operator delete[] (_arrays); } // new
//if (_arrays) delete [] _arrays; // old
Caz
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| SSE in P4 |
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By Diver - Posted on June 15, 2003 - 01:35:26 (#7742)
Current version when comment was posted: 0.1 |
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Hi Caz,
I've compiled and run this app
int main()
{
asm("xorps %xmm0, %xmm0"); //
return 0;
}
and it doesn't crash. Does it 100% mean that SSE is enabled? I didn't know that R5 support SSE with new CPUs. Is that true? Oh, BTW, why do gcc 2.95.3 needed to compile this app, and what is the best compiler: R5 original, 2.95.3 or geekgadgets? Thanks for your detailed answer.
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| re: Diver |
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By Caz - Posted on June 14, 2003 - 18:25:19 (#7736)
Current version when comment was posted: 0.1 |
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Hi,
Doesn't BeOS enable SSE on P4's already ?, also the only thing needed to allow BeOS to use SSE is to enable bit 9 of the cr4 register, the AthlonXpSSEenable app does this but if you try to disable SSE and BeOS has it enabled already then your machine will hang or reboot. You can also make a simple app and if it doesn't crash then SSE is enabled,
int main()
{
asm("xorps %xmm0, %xmm0"); // gcc 2.95.3 needed
return 0;
}
Anyway you can modify the driver.c file in AthlonXpSSEenable like this, delete the old EnableXpSSE/DisableXpSSE code and paste this and rebuild. The MSR_K7_HWCR isn't needed for P3/P4.
static void EnableXpSSE()
{
//unsigned long l, h;
set_in_cr4(X86_CR4_OSXMMEXCPT);
set_in_cr4(X86_CR4_OSFXSR);
//rdmsr(MSR_K7_HWCR, l, h);
//l &= ~0x00008000;
//wrmsr(MSR_K7_HWCR, l, h);
}
static void DisableXpSSE()
{
//unsigned long l, h;
clear_in_cr4(X86_CR4_OSXMMEXCPT);
clear_in_cr4(X86_CR4_OSFXSR);
//rdmsr(MSR_K7_HWCR, l, h);
//l |= 0x00008000;
//wrmsr(MSR_K7_HWCR, l, h);
}
Caz
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| SSE in P4 |
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By Diver - Posted on June 14, 2003 - 03:06:51 (#7725)
Current version when comment was posted: 0.1 |
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Is it possible to make SSE enable driver for Pentium 4?
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